
`include "common_header.verilog"

//  *************************************************************************
//  File : redge_ckxing_tog
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized Reproduction or Use is Expressly Prohibited. 
//  Copyright (c) 2002 MoreThanIP.com, Germany
//  info@morethanip.com
//  Designed by : Daniel Koehler
//  *************************************************************************                    
//  Description: Convert rising edge input signal from input clock domain into 
//               pulse within output clock domain using a toggling signal.
//               That is, no return feedback is needed.
//  Version    : $Id: redge_ckxing_tog.v,v 1.2 2015/09/23 20:39:40 dp Exp $
//  *************************************************************************
module redge_ckxing_tog (
   
   reset,
   clk,
   sig,
   reset_clk_o,
   clk_o,
   sig_o);

input   reset; 
input   clk; 
input   sig;            //  pulse or active high input
input   reset_clk_o; 
input   clk_o; 
output  sig_o;          //  always a single clock pulse output

reg     sig_o; 

//  Input clock domain
reg     in_reg; 
reg     in_tog; 
//  clk_o domain
wire    out_reg_s1; //  domain crossing 
reg     out_reg_s2; //  domain crossing 

//  input clock domain
//  ------------------

always @(posedge reset or posedge clk)
   begin : ind
   if (reset == 1'b 1)
      begin
      in_reg <= 1'b 0;	
      in_tog <= 1'b 0;	
      end
   else
      begin
      in_reg <= sig;	
      if (sig == 1'b 1 & in_reg == 1'b 0)       // rising edge
         begin
         in_tog <= ~in_tog;	
         end
      end
   end

//  output clock domain
//  -------------------
always @(posedge reset_clk_o or posedge clk_o)
   begin : op
   if (reset_clk_o == 1'b 1)
      begin	
      out_reg_s2 <= 1'b 0;	
      sig_o <= 1'b 0;	
      end
   else
      begin
      out_reg_s2 <= out_reg_s1;	
        //  pulse forming
      sig_o <= out_reg_s1 ^ out_reg_s2;	
      end
   end



mtip_xsync  #(1) U_RESYNC_OUTPUT (
        .data_in        (in_tog),
        .reset          (reset_clk_o),
        .clk            (clk_o),
        .data_s         (out_reg_s1));








endmodule // module redge_ckxing_tog
